256Mb: 3V Embedded Parallel NOR Flash
Features
Micron Parallel NOR Flash Embedded
Memory
M29DW256G X16 Multiple Bank, Page, Dual Boot 3V Supply Flash
Memory
Features
• VPP/WP# pin for fast program and write
– Protects the four outermost parameter blocks
• Software protection
– Volatile protection
– Nonvolatile protection
– Password protection
• Extended memory block
– Programmed or locked at the factory or by the
customer
– 128 word factory locked and 128 word customer
lockable
• Common flash interface
– 64-bit security code
• Low power consumption: standby and automatic
mode
• 100,000 minimum PROGRAM/ERASE cycles per
block
• Data retention: 20 years (TYP)
• Fortified BGA, TBGA, and TSOP packages
• Green packages available
– RoHS-compliant
– Halogen-free
• Automotive certified parts available
– Automotive device grade: temperature –40°C to
+85°C (automotive grade certified)
• Root part number
– M29DW256G
• Device code
– 227Eh + 223Ch + 2202h
• Supply voltage
– VCC = 2.7–3.6V (program, erase, read)
– VCCQ = 1.65–3.6V (I/O buffers)
– VPPH = 9V for fast program (optional)
• Asynchronous random/page read
– Page size: 8 words
– Page access: 25ns, 30ns
– Random access: 70ns, 80ns
• Fast program commands: 32-word
• Enhanced buffered program commands: 256-word
• Program time
– 16µs per byte/word TYP
– Chip program time: 10 s with V PPH and 16s without V PPH
• Memory organization
– Quadruple bank memory array: 32Mb + 96Mb +
96Mb + 32Mb with parameter blocks at top and
bottom
– Dual operation: program/erase in one bank
while reading in any other bank
• Program/erase controller
– Embedded word program algorithms
• Program/erase suspend and resume capability
– Read from any block during a PROGRAM SUSPEND operation
– Read or program another block during an ERASE
SUSPEND operation
• Unlock bypass, block erase, chip erase, write to buffer, and enhanced buffer program commands
– Fast buffered/batch programming
– Fast block/chip erase
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256Mb: 3V Embedded Parallel NOR Flash
Features
Part Numbering Information
Available with extended memory block prelocked by Micron. Devices are shipped from the factory with memory
content bits erased to 1. For available options, such as packages or high/low protection, or for further information,
contact your Micron sales representative. Part numbers can be verified at www.micron.com. Feature and specification comparison by device type is available at www.micron.com/products. Contact the factory for devices not
found.
Table 1: Part Number Information
Part Number
Category
Category Details
Notes
Device Type
M29
Architecture
D = Dual operation
Operating Voltage
W = VCC = 2.7 to 3.6V
Device function
256G = 256Mb (x16) page, dual boot
Speed
70 = 70ns
1, 2
7A = 70ns
1, 2
Package
NF = 56-pin TSOP, 14mm x 20mm, lead-free, halogen-free, RoHS-compliant
ZA = 64-pin TBGA, 10mm x 13mm, lead-free, halogen-free, RoHS-compliant
ZS = 64-pin Fortified BGA, 11mm x 13mm, lead-free, halogen-free, RoHS-compliant
Temperature Range
1 = 0 to 70°C
6 = –40°C to +85°C
Shipping Options
E = RoHS-compliant package, standard packing
F = RoHS-compliant package, tape and reel packing
Notes:
1. 80ns if VCCQ = 1.65V to VCC.
2. Automotive certified –40°C to +85°C, available only with option 6.
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256Mb: 3V Embedded Parallel NOR Flash
Features
Contents
Important Notes and Warnings ......................................................................................................................... 7
Description ...................................................................................................................................................... 7
Signals ......................................................................................................................................................... 9
Signal Assignments ......................................................................................................................................... 10
Signal Descriptions ......................................................................................................................................... 12
Memory Organization .................................................................................................................................... 14
Memory Configuration ............................................................................................................................... 14
Block Addresses and Protection Groups ....................................................................................................... 15
Bus Operations ............................................................................................................................................... 19
Read .......................................................................................................................................................... 19
Write .......................................................................................................................................................... 19
Standby and Automatic Standby ................................................................................................................. 19
Output Disable ........................................................................................................................................... 20
Reset .......................................................................................................................................................... 20
Registers ........................................................................................................................................................ 21
Status Register ............................................................................................................................................ 21
Lock Register .............................................................................................................................................. 26
Standard Command Definitions – Address-Data Cycles .................................................................................... 28
READ and AUTO SELECT Operations .............................................................................................................. 31
READ/RESET Command ............................................................................................................................ 31
READ CFI Command .................................................................................................................................. 31
UNLOCK BYPASS READ CFI Command ....................................................................................................... 31
AUTO SELECT Command ........................................................................................................................... 31
Bypass Operations .......................................................................................................................................... 33
UNLOCK BYPASS Command ...................................................................................................................... 33
UNLOCK BYPASS RESET Command ............................................................................................................ 33
Program Operations ....................................................................................................................................... 34
PROGRAM Command ................................................................................................................................ 34
UNLOCK BYPASS PROGRAM Command ..................................................................................................... 34
WRITE TO BUFFER PROGRAM Command .................................................................................................. 34
UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command ....................................................................... 37
WRITE TO BUFFER PROGRAM CONFIRM Command .................................................................................. 37
BUFFERED PROGRAM ABORT AND RESET Command ................................................................................ 37
PROGRAM SUSPEND Command ................................................................................................................ 37
PROGRAM RESUME Command .................................................................................................................. 38
WRITE TO BUFFER PROGRAM SUSPEND Command .................................................................................. 38
WRITE TO BUFFER PROGRAM RESUME Command .................................................................................... 39
ENTER ENHANCED BUFFERED Command ................................................................................................ 39
ENHANCED BUFFERED PROGRAM Command ........................................................................................... 39
ENHANCED BUFFERED PROGRAM ABORT RESET Command .................................................................... 40
EXIT ENHANCED BUFFERED PROGRAM Command ................................................................................... 42
Erase Operations ............................................................................................................................................ 43
CHIP ERASE Command .............................................................................................................................. 43
UNLOCK BYPASS CHIP ERASE Command ................................................................................................... 43
BLOCK ERASE Command ........................................................................................................................... 43
UNLOCK BYPASS BLOCK ERASE Command ................................................................................................ 44
ERASE SUSPEND Command ....................................................................................................................... 44
ERASE RESUME Command ........................................................................................................................ 45
Block Protection Command Definitions – Address-Data Cycles ........................................................................ 46
Protection Operations .................................................................................................................................... 48
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256Mb: 3V Embedded Parallel NOR Flash
Features
LOCK REGISTER Commands ......................................................................................................................
PASSWORD PROTECTION Commands .......................................................................................................
NONVOLATILE PROTECTION Commands ..................................................................................................
NONVOLATILE PROTECTION BIT LOCK BIT Commands ............................................................................
VOLATILE PROTECTION Commands ..........................................................................................................
EXTENDED MEMORY BLOCK Commands ..................................................................................................
EXIT PROTECTION Command ....................................................................................................................
Device Protection ...........................................................................................................................................
Hardware Protection ..................................................................................................................................
Software Protection ....................................................................................................................................
Volatile Protection Mode .............................................................................................................................
Nonvolatile Protection Mode ......................................................................................................................
Password Protection Mode ..........................................................................................................................
Dual Operations and Multiple Bank Architecture .............................................................................................
Common Flash Interface ................................................................................................................................
Power-Up and Reset Characteristics ................................................................................................................
Absolute Ratings and Operating Conditions .....................................................................................................
DC Characteristics ..........................................................................................................................................
Read AC Characteristics ..................................................................................................................................
Write AC Characteristics .................................................................................................................................
Accelerated Program, Data Polling/Toggle AC Characteristics ...........................................................................
Program/Erase Characteristics ........................................................................................................................
Package Dimensions .......................................................................................................................................
Revision History .............................................................................................................................................
Rev. B – 5/18 ...............................................................................................................................................
Rev. A – 10/12 .............................................................................................................................................
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67
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256Mb: 3V Embedded Parallel NOR Flash
Features
List of Figures
Figure 1: Logic diagram ................................................................................................................................... 9
Figure 2: 56-Pin TSOP (Top View) .................................................................................................................. 10
Figure 3: 64-Pin Fortified BGA and 64-Pin TBGA ............................................................................................. 11
Figure 4: Block Addresses .............................................................................................................................. 14
Figure 5: Data Polling Flowchart .................................................................................................................... 23
Figure 6: Toggle Bit Flowchart ........................................................................................................................ 24
Figure 7: Status Register Polling Flowchart ..................................................................................................... 25
Figure 8: Lock Register Program Flowchart ..................................................................................................... 27
Figure 9: WRITE TO BUFFER PROGRAM Flowchart ........................................................................................ 36
Figure 10: ENHANCED BUFFERED PROGRAM Flowchart ............................................................................... 41
Figure 11: Program/Erase Nonvolatile Protection Bit Algorithm ...................................................................... 50
Figure 12: Software Protection Scheme .......................................................................................................... 56
Figure 13: Power-Up Timing .......................................................................................................................... 62
Figure 14: Reset AC Timing – No PROGRAM/ERASE Operation in Progress ...................................................... 63
Figure 15: Reset AC Timing During PROGRAM/ERASE Operation .................................................................... 63
Figure 16: AC Measurement Load Circuit ....................................................................................................... 65
Figure 17: AC Measurement I/O Waveform ..................................................................................................... 65
Figure 18: Random Read AC Timing ............................................................................................................... 67
Figure 19: Page Read AC Timing ..................................................................................................................... 68
Figure 20: WE#-Controlled Program AC Timing .............................................................................................. 70
Figure 21: CE#-Controlled Program AC Timing ............................................................................................... 72
Figure 22: Accelerated Program AC Timing ..................................................................................................... 73
Figure 23: Data Polling AC Timing .................................................................................................................. 74
Figure 24: Toggle/Alternative Toggle Bit Polling AC Timing .............................................................................. 74
Figure 25: 56-Pin TSOP – 14mm x 20mm ........................................................................................................ 76
Figure 26: 64-Pin TBGA – 10mm x 13mm ........................................................................................................ 77
Figure 27: 64-Ball Fortified BGA – 11mm x 13mm ........................................................................................... 78
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256Mb: 3V Embedded Parallel NOR Flash
Features
List of Tables
Table 1: Part Number Information ................................................................................................................... 2
Table 2: Signal names ...................................................................................................................................... 9
Table 3: Signal Descriptions ........................................................................................................................... 12
Table 4: Bank architecture ............................................................................................................................. 14
Table 5: Bank A ............................................................................................................................................. 15
Table 6: Bank B ............................................................................................................................................. 15
Table 7: Bank C ............................................................................................................................................. 17
Table 8: Bank D ............................................................................................................................................. 18
Table 9: Bus Operations ................................................................................................................................. 19
Table 10: Status Register Bit Definitions ......................................................................................................... 21
Table 11: Operations and Corresponding Bit Settings ...................................................................................... 22
Table 12: Lock Register Bit Definitions ............................................................................................................ 26
Table 13: Block Protection Status ................................................................................................................... 26
Table 14: Standard Command Definitions – Address-Data Cycles, 16-Bit ......................................................... 28
Table 15: Read Electronic Signature, Auto Select Mode and Programmer Method ............................................. 32
Table 16: Block protection (16-bit mode) ........................................................................................................ 32
Table 17: Block Protection Command Definitions – Address-Data Cycles, 16-Bit .............................................. 46
Table 18: Extended Memory Block Address and Data ...................................................................................... 51
Table 19: V PP/WP# Functions ......................................................................................................................... 53
Table 20: Dual Operations Allowed in Other Banks ......................................................................................... 57
Table 21: Dual Operations Allowed in Same Bank ........................................................................................... 58
Table 22: Query Structure Overview ............................................................................................................... 59
Table 23: CFI Query Identification String ........................................................................................................ 59
Table 24: CFI Query System Interface Information .......................................................................................... 60
Table 25: Device Geometry Definition ............................................................................................................ 60
Table 26: Primary Algorithm-Specific Extended Query Table ........................................................................... 61
Table 27: Security Code Area .......................................................................................................................... 61
Table 28: Power-Up Wait Timing Specifications .............................................................................................. 62
Table 29: Reset AC Specifications ................................................................................................................... 63
Table 30: Absolute Maximum/Minimum Ratings ............................................................................................ 64
Table 31: Operating Conditions ...................................................................................................................... 64
Table 32: Input/Output Capacitance1 ............................................................................................................. 65
Table 33: DC Current Characteristics .............................................................................................................. 66
Table 34: DC Voltage Characteristics .............................................................................................................. 66
Table 35: Read AC Characteristics .................................................................................................................. 67
Table 36: WE#-Controlled Write AC Characteristics ......................................................................................... 69
Table 37: CE#-Controlled Write AC Characteristics ......................................................................................... 71
Table 38: Accelerated Program and Data Polling/Data Toggle AC Characteristics .............................................. 73
Table 39: Program/Erase Characteristics ........................................................................................................ 75
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256Mb: 3V Embedded Parallel NOR Flash
Important Notes and Warnings
Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
Description
The M29DW256G is a 256Mb (16Mb x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be performed using a single low voltage (2.7
to 3.6 V) supply. At power-up the memory defaults to its read mode.
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256Mb: 3V Embedded Parallel NOR Flash
Description
The M29DW256G features an asymmetrical block architecture, with 8 parameter and
126 main blocks, divided into four banks, A, B, C and D, providing multiple bank operations. While programming or erasing in one bank, read operations are possible in any
other bank. Four of the parameter blocks are at the top of the memory address space,
and four are at the bottom.
Program and erase commands are written to the command interface of the memory. An
on-chip program/erase controller simplifies the process of programming or erasing the
memory by taking care of all of the special operations that are required to update the
memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable signals control the bus operations of the
memory. They allow simple connection to most microprocessors, often without additional logic.
The device supports asynchronous random read and page read from all blocks of the
memory array. The device also features a write to buffer program capability that improves the programming throughput by programming 32 words in one instance. The
enhanced buffered program feature is also available to speed up programming throughput, allowing 256 words to be programmed at once. The V PP/WP# signal can be used to
enable faster programming of the device.
The M29DW256G has one extra 256-word extended block that can be accessed using a
dedicated command: 128-Word factory locked and 128-Word customer lockable. The
extended block can be protected and so is useful for storing security information. However the protection is irreversible; once protected the protection cannot be undone.
The device features different levels of hardware and software block protection to avoid
unwanted program or erase (modify):
• Hardware protection: V PP/WP# provides hardware protection on four outermost parameter blocks (two at the top and two at the bottom of the address space)
• Software protection: Volatile protection, nonvolatile protection, password protection
The memory is offered in TSOP56 (14mm x 20mm), TBGA64 (10mm x 13mm, 1mm
pitch), and FBGA (11mm x 13mm) packages. The memory is delivered with all the bits
erased (set to ‘1’).
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256Mb: 3V Embedded Parallel NOR Flash
Description
Signals
Table 2: Signal names
Name
Description
Direction
A[23:0]
Address inputs
Inputs
DQ[15:0]
Data inputs/outputs
I/O
CE#
Chip enable
Input
OE#
Output enable
Input
WE#
Write enable
Input
RST#
Reset
Input
RY/BY#
Ready/busy output
Output
VCCQ
Input/output buffer supply voltage
Supply
VCC
Supply voltage
Supply
VPP/WP#
VPP/write protect
Supply/Input
VSS
Ground
–
NC
Not connected
–
Note:
1.
1
VPP/WP# may be left floating as it is internally connected to a pull-up resistor which
enables program/erase operations.
Figure 1: Logic diagram
VCC
VCCQ
A[23:0]
VPP/WP#
DQ[15:0]
WE#
CE#
OE#
RY/BY#
RST#
NC
VSS
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256Mb: 3V Embedded Parallel NOR Flash
Signal Assignments
Signal Assignments
Figure 2: 56-Pin TSOP (Top View)
A23
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RST#
A21
VPP/WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
RFU
RFU
Note:
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55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
RFU
RFU
A16
RFU
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
RFU
VCCQ
1. A[23] = A[MAX].
10
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256Mb: 3V Embedded Parallel NOR Flash
Signal Assignments
Figure 3: 64-Pin Fortified BGA and 64-Pin TBGA
1
3
2
4
5
7
6
8
8
7
6
5
4
3
2
1
A
A
RFU
A3
A7 RY/BY# WE#
A9
A13
RFU
RFU
A13
A9
WE# RY/BY# A7
A3
RFU
B
B
RFU
A4
A17 VPP/WP# RST#
A8
A12
A22
A22
A12
A8
RST# VPP/WP# A17
A4
RFU
C
C
RFU
A2
A6
A18
A21
A10
A14
A23
A23
A14
A10
A21
A18
A6
A2
RFU
D
D
RFU
A1
A5
A20
A19
A11
A15 VCCQ
VCCQ A15
A11
A19
A20
A5
A1
RFU
E
E
A0
D0
D2
D5
D7
A16
VSS
VSS
VCCQ CE#
D8
D10
D12
D14
RFU
RFU
RFU
RFU
D14
D12
D10
D8
CE# VCCQ
RFU
OE#
D9
D11
VCC
D13
D15
RFU
RFU
D15
D13
VCC
D11
D9
OE#
RFU
RFU
VSS
D1
D3
D4
D6
VSS
RFU
RFU
VSS
D6
D4
D3
D1
VSS
RFU
RFU
A16
D7
D5
D2
D0
A0
RFU
F
F
G
G
H
H
Top view – ball side down
Note:
CCMTD-1725822587-2414
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Bottom view – ball side up
1. A[23] = A[MAX].
11
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256Mb: 3V Embedded Parallel NOR Flash
Signal Descriptions
Signal Descriptions
The signal description table below is a comprehensive list of signals for this device family. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device.
Table 3: Signal Descriptions
Name
Type
Description
A[MAX:0]
Input
Address: Selects the cells in the array to access during READ operations. During WRITE operations, they control the commands sent to the command interface of the program/erase controller.
DQ[15:0]
I/O
Data I/O: Outputs the data stored at the selected address during a READ operation. During
WRITE operations, they represent the commands sent to the command interface of the internal state machine. During WRITE operations, bits DQ[15:8] are not used. When reading the
status register, these bits should be ignored.
CE#
Input
Chip enable: Activates the device, enabling READ and WRITE operations to be performed.
When CE# is HIGH, the device goes to standby and data outputs are at HIGH-Z.
OE#
Input
Output enable: Controls the bus READ operation.
WE#
Input
Write enable: Controls the bus WRITE operation of the command interface.
VPP/WP#
Input
VPP/Write Protect: Provides two functions. The VPPH function enables the device to bypass
unlock cycles and use an external high voltage power supply to reduce time required for
PROGRAM operations.
Second, When VPP/WP# is LOW, the four outermost blocks of the address space (two 32KW
blocks at the top and two 32KW blocks at the bottom) are protected; PROGRAM and ERASE
operations are ignored and the blocks remain protected regardless of the block protection
status or the RST# pin state. When VPP/WP# is HIGH, the memory reverts to the previous protection status for those blocks (Refer to Hardware Protection and Bypass Operations for details).
RST#
Input
Reset: Applies a hardware reset to the device, which is achieved by holding RST# LOW for at
least tPLPX. After RST# goes HIGH, the device is ready for READ and WRITE operations (after
tPHEL or tRHEL, whichever occurs last). See RESET AC Specifications for more details.
RY/BY#
Output
Ready busy: Open-drain output that can be used to identify when the device is performing
a PROGRAM or ERASE operation. During PROGRAM or ERASE operations, RY/BY# is LOW,
and is High-Z during read mode, auto select mode, and erase suspend mode. After a hardware reset, READ and WRITE operations cannot begin until RY/BY# goes High-Z (see RESET
AC Specifications for more details).
The use of an open-drain output enables the RY/BY# pins from several devices to be connected to a single pull-up resistor to VCCQ. A low value will then indicate that one or more of the
devices is busy.
VCC
Supply
Supply voltage: Provides the power supply for READ, PROGRAM, and ERASE operations.
The command interface is disabled when VCC
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